1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing thereof. In particular, the present invention relates to a semiconductor device having an STI (Shallow Trench Isolation) structure and a method of manufacturing thereof.
2. Description of the Related Art
In a semiconductor device such as a DRAM or the like, a device isolation structure is formed in order to isolate elements from one another. An STI structure is well known as the device isolation structure, in which a trench on a substrate is filled with an insulating film.
FIG. 1 is a cross-sectional view illustrating a conventional STI structure. As shown in FIG. 1, a silicon substrate 101 is provided with a trench 105. The trench 105 is filled with an STI structure 140 as the device isolation structure. More specifically, a silicon thermal oxide film 110 is formed on a surface of the silicon substrate 101 in the trench 105. In addition, a CVD oxide film 120 is formed on the silicon thermal oxide film 110. That is to say, a surface of the trench 105 is covered with the silicon thermal oxide film 110, and the other region within the trench 105 is filled with the CVD oxide film 120. The silicon thermal oxide film 110 and the CVD oxide film 120 form the STI structure 140.
Moreover, as shown in FIG. 2, a silicon nitride film (SiN film) 130 may be formed between the silicon thermal oxide film 110 and the CVD oxide film 120 (for example, refer to Japanese Laid-Open Patent Application JP-P2005-322859). In this case, the silicon thermal oxide film 110, the silicon nitride film 130 and the CVD oxide film 120 form the STI structure 140.
As shown in FIGS. 1 and 2, the device isolation is achieved by the STI structure 140 and an active region Ra of a transistor is so formed as to be surrounded by adjacent STI structures 140. Here, a width of the active region Ra, namely, an interval between the adjacent STI structures 140 is “W2”.
A method of manufacturing the conventional STI structure 140 described above is as follows. For example, FIGS. 3 to 7 sequentially show processes of manufacturing the STI structure 140 illustrated in FIG. 1.
First, as shown in FIG. 3, a silicon thermal oxide film 102 and a silicon nitride film 103 are deposited in series on the silicon substrate 101. Further, a resist mask 104 having a predetermined pattern is formed on the silicon nitride film 103 by the photolithography technique.
Next, the silicon nitride film 103 and the silicon thermal oxide film 102 at an opening of the resist mask 104 are removed by a dry etching using the resist mask 104. Then, the resist mask 104 is removed. As a result, an SiN mask 106 for forming a trench is formed, as shown in FIG. 4. Subsequently, a dry etching of the silicon substrate 101 is performed by using the SiN mask 106. Consequently, as shown in FIG. 4, the trench 105 is formed at a region where the STI structure is embedded. At this point, an interval between adjacent trenches 105, namely, a width of a region corresponding to the active region Ra is “W1”.
Next, as shown in FIG. 5, the silicon thermal oxide film 110 with a thickness of about 10 nm is formed on the exposed surface of the trench 105 by a thermal oxidation method. The thermal oxidation recovers damages on the substrate surface that have been generated by the dry etching (trench etching) for forming the above-mentioned trench 105 (refer to Japanese Laid-Open Patent Application JP-P2005-322859). It is said that junction leakage characteristic is improved due to the damage recovery. As a result of the thermal oxidation of the substrate surface, the width of the active region Ra becomes “W2” that is narrower than the above-mentioned “W1”.
Next, as shown in FIG. 6, a CVD oxide film 115 is deposited by a high-density plasma CVD (HDP-CVD) method such that the inside of the trench 105 is completely filled with the CVD oxide film 115. Here, the above-mentioned silicon oxide film 110 covering the surface of the trench 105 plays a role of protecting the substrate surface from the high-density plasma.
Next, as shown in FIG. 7, the surplus CVD oxide film 115 is removed by CMP (Chemical Mechanical Polishing) and the CVD oxide film 120 of the STI structure is formed. Here, the SiN mask 106 is used as a stopper. After that, the SiN mask 106 and a part of the CVD oxide film 120 are removed by a wet etching. As a result, the STI structure 140 shown in FIG. 1 is obtained.
According to the conventional technique, as described above, the silicon thermal oxide film 110 covering the surface of the trench 105 is formed by the direct thermal oxidation of the exposed surface of the trench 105. Consequently, the damages on the substrate surface caused by the trench etching are recovered, and moreover the substrate surface is protected during the HDP-CVD process. Thus, the junction leakage characteristic is prevented from deterioration.